In plasma processing of semiconductor wafers, precise feature profile control has become increasingly important during gate etching as the critical dimensions of semiconductor devices continue to scale down below 45 nm. For example, the integrity and critical dimension (CD) control of the hardmask during gate mask definition is critical in gate etch applications. For example, for a polysilicon gate, the hardmask layer overlying the polysilicon layer can be silicon nitride. For etching of the silicon nitride hardmask layer, the CD of greatest criticality is the mask length at the bottom of the hardmask. Likewise, for etching of the polysilicon gate, the CD of greatest criticality is the gate length at the bottom of the polysilicon gate. This length typically defines the all-important channel length of the transistor during later process steps. Therefore, during definition (etching) of the hardmask or of the polysilicon gate, it is important to minimize discrepancy between the required CD and the CD obtained at the end of the etch step. It is also important to minimize the variation in the CD bias, the difference between the CD as defined by the mask and the final CD after the etch process. Finally, it is important to minimize the CD bias microloading, which is the difference between the CD bias in regions in which the discrete circuit features are dense or closely spaced and the CD bias in regions in which the discrete circuit features are isolated or widely spaced apart.
Various conventional techniques have been used to meet these requirements. For instance, trial-and-error techniques have been used for determining the optimum gas flow rates for the various gas species in the reactor, the optimum ion energy (determined mainly by RF bias power on the wafer) and the optimum ion density (determined mainly by RF source power on the coil antenna). The foregoing process parameters affect not only CD, CD bias and CD bias microloading but also affect other performance parameters, such as etch rate and etch rate uniformity. It may not be possible to set the process parameters to meet the required performance parameters such as etch rate and at the same time optimize CD and minimize CD bias and CD bias microloading. As a result, the process window, e.g., the allowable ranges of process parameters such as chamber pressure, gas flow rates, ion energy and ion density, may be unduly narrow to satisfy all requirements.
A current problem is that CD bias is non-uniform, decreasing near the wafer edge. This problem is becoming more acute as device feature sizes are scaled down to 32 nm and smaller. Part of this problem is the sharp drop in CD bias at the wafer edge. We believe that this sharp drop is due to the lack of etch passivation species to passivate etch by-products. The amount of passivation species affects etch profile tapering and sidewall etch rate in high aspect ratio openings. Typically, the greater the amount of passivation gas present, the greater the etch profile tapering. What is desired is the etch profile or etch profile tapering be uniform across the wafer. This will promote a uniform distribution of CD bias. Because of the lack of passivation gas at the wafer edge, the etch profile taper is small at the wafer edge and large elsewhere.